Computer organization mcqs cache miss hit
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Question 1 [CLICK ON ANY COICE TO KNOW RIGHT ANSWER] |
The main memory is structured into modules each with its own address register called .....
ABR | |
TLB | |
PC | |
IR |
Question 1 Explanation:
ABR stands for Address Buffer Register.
Question 2 [CLICK ON ANY COICE TO KNOW RIGHT ANSWER] |
When consecutive memory locations are accessed only one module is accessed at a time.
True | |
False |
Question 2 Explanation:
In a modular approach to memory structuring only one module can be accessed at a time.
Question 3 [CLICK ON ANY COICE TO KNOW RIGHT ANSWER] |
In memory interleaving, the lower order bits of the address is used to .....
Get the data | |
Get the address of the module | |
Get the address of the data within the module | |
None of the mentioned |
Question 3 Explanation:
To implement parallelism in data access we use interleaving.
Question 4 [CLICK ON ANY COICE TO KNOW RIGHT ANSWER] |
The number successful accesses to memory stated as a fraction is called as .....
Hit rate | |
Miss rate | |
Success rate | |
Access rate |
Question 4 Explanation:
The hit rate is an important factor in performance measurement.
Question 5 [CLICK ON ANY COICE TO KNOW RIGHT ANSWER] |
The number failed attempts to access memory, stated in the form of a fraction is called as .....
Hit rate | |
Miss rate | |
Failure rate | |
Delay rate |
Question 5 Explanation:
The miss rate is a key factor in deciding the type of replacement algorithm.
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