Computer organization mcqs performance caches
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The memory transfers between two variable speed devices are always done at the speed of the faster device.
An effective to introduce parallelism in memory access is by .....
Question 7 Explanation:
Interleaving divides the memory into modules.
The performance of the system is greatly influenced by increasing the level 1 cache.
Question 8 Explanation:
This is so because the L1 cache is onboard the processor.
Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster.
Both take the same time
If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is a term of the Basic performance equation).
Question 10 Explanation:
Pipelining is a process of fetching an instruction during the execution of other instruction.
There are 10 questions to complete.